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technical note single-chip type with built-in fet switching regulator series low noise step-down high efficiency step-down switching regulator with built-in power mosfet BD8962MUV description rohm?s high efficiency step-down switching regulator BD8962MUV is a power supply designed to produce a low voltage including 0.8 volts from 5.5/3.3 volts power supply line. offe rs high efficiency with synchronous rectifier. employs a curren t mode control system to provide faster tr ansient response to sudden change in load. features 1) offers fast transient response with current mode pwm control system. 2) offers highly efficiency for all load range with synchronous rectifier (nch/nch fet) 3) incorporates soft-start function. 4) incorporates thermal protection and ulvo functions. 5) incorporates short-current protec tion circuit with time delay function. 6) incorporates shutdown function icc=0 a(typ.) 7) employs small surface mount package : vqfn020v4040 use power supply for lsi including dsp, micro computer and asic absolute maximu m rating (ta=25 ) parameter symbol limits unit BD8962MUV v cc voltage v cc -0.3 +7 * 1 v pv cc voltage pv cc -0.3 +7 * 1 v bst voltage v bst -0.3 +13 v bst_sw voltage v bst - sw -0.3 +7 v en voltage ven -0.3 +7 v sw,ith voltage vsw, vith -0.3 +7 v power dissipation 1 pd1 0.34 * 2 w power dissipation 2 pd2 0.70 * 3 w power dissipation 3 pd3 1.21 * 4 w power dissipation 4 pd4 3.56 * 5 w operating temperature range topr -40 +105 storage temperature range ts t g -55 +150 maximum junction temperature tj +150 1 pd should not be exceeded. 2 ic only 3 1-layer. mounted on a 74.2mm 74.2mm 1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm 2 4 4-layer. mounted on a 74.2mm 74.2mm 1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm 2 , in each layers 5 4-layer. mounted on a 74.2mm 74.2mm 1.6mm glass-epoxy board, occupied area by copper foil : 5505mm 2 , in each layers operating conditions (ta=-40 +105 ) parameter symbol BD8962MUV unit min. typ. max. power supply voltage v cc 2.7 3.3 5.5 v pv cc 2.7 3.3 5.5 v en voltage ven 0 - 5.5 v output voltage setting range v out 0.8 - 2.5* 6 v sw average output current i sw - - 3.0* 7 a 6 in case set output voltage 1.6v or more, vccmin = vout+1.2v . 7 pd should not be exceeded. jul. 2008
2/16 electrical characteristics BD8962MUV (ta=25 v cc =pv cc =3.3v, en=v cc , r 1 =10k , r 2 =5k ,unless otherwise specified.) parameter symbol min. typ. max. unit conditions standby current i stb - 0 10 a en=gnd active current i cc - 250 500 a en low voltage v enl - gnd 0.8 v standby mode en high voltage v enh 2.0 vcc - v active mode en input current i en - 1 10 a v en =3.3v oscillation frequency f osc 0.8 1 1.2 mhz high side fet on resistance r onh - 82 115 m pv cc =3.3v low side fet on resistance r onl - 70 98 m pv cc =3.3v adj voltage v adj 0.788 0.800 0.812 v ith si nk current i thsi 10 18 - a v adj =1v ith s ource c urrent i thso 10 18 - a v adj =0.6v uvlo threshold voltage v uvlo1 2.400 2.500 2.600 v v cc =3.3v 0v uvlo release voltage v uvlo2 2.425 2.550 2.700 v v cc =0v 3.3v soft start time t ss 2.5 5 10 ms timer latch time t latch 0.5 1 2 ms output short circuit threshold voltage v scp - 0.40 0.56 v v adj =0.8v 0v block diagram, application circuit BD8962MUV pin no. & function table pin no. pin name function pin no. pin name function 1 sw sw pin 11 gnd ground 2 sw sw pin 12 adj output voltage detect pin 3 sw sw pin 13 ith gmamp output pin/connected phase compensation capacitor 4 sw sw pin 14 n.c. non connection 5 sw sw pin 15 n.c. non connection 6 pvcc highside fet source pin 16 n.c. non connection 7 pvcc highside fet source pin 17 en enable pin(high active 8 pvcc highside fet source pin 18 pgnd lowside fet source pin 9 bst bootstrapped voltage input pin 19 pgnd lowside source pin 10 vcc vcc power supply input pin 20 pgnd lowside source pin fig.2 BD8962MUV block diagram fig.1 BD8962MUV top view output pgnd gnd gm amp r s q osc uvlo tsd + v cc v cc clk slope en current comp soft start current sense/ protect + driver logic + vref ith a dj r ith c ith r1 r2 pv cc sw pv cc bst v cc input scp (unit : mm) 2.1 0.1 c0.2 0.5 1.0 15 6 10 11 15 16 20 4.0 0.1 4.0 0.1 2.1 0.1 0.4 0.1 0.25 +0.05 -0.04 0.02 +0.03 -0.02 1.0max. (0.22) 0.08 s s d8962 lot no.
3/16 characteristics data BD8962MUV 0.0 0.4 0.8 1.2 1.6 2.0 012345678 output current:i out [a] output voltage:vout[v] 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 10000 output current:i out [ma] efficiency: [%] 0.7 0.8 0.9 1 1.1 2.7 3.4 4.1 4.8 5.5 input voltage:v cc [v] frequency:f osc [mhz] 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -40 -20 0 20 40 60 80 100 temperature:ta[ ] en voltage:ven[v] fig.10 fig.11 ta - v en 0 50 100 150 200 250 300 350 400 -40 -20 0 20 40 60 80 100 temperature:ta[ ] circuit current:i cc [ a] fig.11 ta - icc vcc=5v vcc=5v 1.18 1.19 1.20 1.21 1.22 -40-200 20406080100 temperature:ta[ ] output voltage:vout[v] 0 200 400 600 800 1000 1200 -40 -20 0 20 40 60 80 100 temperature:ta[ ] frequency:f osc [mhz] fig.8 ta - fosc fig.7 efficiency 0.0 0.4 0.8 1.2 1.6 2.0 012345 input voltage:v cc [v] output voltage:vout[v] fig.3 vcc - v out fig.5 i out - v out v out i out v out i out vcc=5 v ta = 2 5 v out =1.2v fig. 16 transient response io=1 3a(10 s) vcc=5v ta = 2 5 v out =1.2v fig.17 transient response io=3 1a(10 s) sw v out vcc=5v ta = 2 5 pwm v out =1.2v v out =1.2v v out =1.2v vcc=5v ta = 2 5 vcc=5v io=0a v out =1.2v vcc=5v 0 25 50 75 100 125 150 -40 -20 0 20 40 60 80 100 temperature:ta[ ] on resistance:r on [ ] vcc=3.3v ta = 2 5 fig.12 vcc - fosc fig.9 ta ? r onn , r onp v out =1.2v vcc=5 v ta = 2 5 io=0 a v out v cc =pv cc =en fig.13 soft start waveform fig.14 sw waveform io=10ma fig. 6 ta - v out ta = 2 5 io=3a 0.0 0.4 0.8 1.2 1.6 2.0 01 23 45 en voltage:ven[v] output voltage:vout[v] vcc=5v ta = 2 5 io=0a v out =1.2v fig.4 v en - v out high side low side vcc=5v ta = 2 5 vout=1.2
4/16 information on advantages advantage 1 offers fast transient response with current mode control system. voltage drop due to sudden change in load was reduced by about 50%. fig.18 comparison of transient response advantage 2 offers high efficiency for all load range with synchronous rectifier. utilizes the synchronous rectifyi ng mode and the low on-resistance mos fets incorporated as power transistor. on resistance of highside mos fet : 82m (typ.) on resistance of lowside mos fet : 70m (typ.) advantage 3 ? supplied in smaller package due to small-sized power mos fet incorporated. reduces a mounting area required. fig.20 example application fig.19 efficiency conventional product (load response i o =1a 3a) BD8962MUV (load response i o =1a 3a) ? output capacitor co required for current mode control: 22 f ceramic capacitor ? inductance l required for the oper ating frequency of 1 mhz: 2.2 h inductor ? incorporates fet + boot strap diode v out i out 145mv v out i out 62mv output pgnd gnd gm amp r s q osc uvlo tsd + v cc vcc clk slope en current comp soft start current sense/ protect + driver logic + vref ith adj r ith c ith r1 r2 pvcc sw pvcc bst vcc 3.3v input scp 15mm 20mm r 2 c ith c f co l r 1 r ith rf c bst c in 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 10000 output current:i out [ma] efficiency: [%] vcc=5v ta = 2 5 vout=1.2
5/16 operation BD8962MUV is a synchronous rectifying step- down switching regulator that achieves faster transient response by employing current mode pwm control system. synchronous rectifier it does not require the power to be dissipated by a rectifier ex ternally connected to a conventional dc/dc converter ic, and it s p.n junction shoot-through protection circuit limits the shoot-through current during op eration, by which the power dissipation of the set is reduced. current mode pwm control synthesizes a pwm control signal with a inductor current feedback loop added to the voltage feedback. ? pwm (pulse width modulation) control the oscillation frequency for pwm is 1 mhz. set signal form osc turns on a highside mos fet (while a lowside mos fet is turned off), and an inductor current i l increases. the current comparator (curr ent comp) receives two signals, a current feedback control signal (sense: voltage converted from i l ) and a voltage feedback control signal (fb), and issues a reset signal if both input signals are identical to each other, and turn s off the highside mos fet (while a lowside mos fet is turned on) for the rest of the fixed period. t he pwm control repeat this operation. fig.21 diagram of current mode pwm control osc level shift driver logic rq s i l sw ith current comp gm amp. set reset fb load sense v out v out fi g. 22 pwm sw i tc hi ng t i m i ng c h art current comp set reset sw v out pvcc gnd gnd gnd i l (ave) v out (ave) sense fb i l
6/16 description of operations ? soft-start function en terminal shifted to ?high? activates a soft-starter to gradu ally establish the output voltag e with the current limited durin g startup, by which it is possible to prevent an ov ershoot of output voltage and an inrush current. ? shutdown function with en terminal shifted to ?low?, the device turns to standb y mode, and all the function blocks including reference voltage circuit, internal oscillator and drivers are turned to off. circuit current during standby is 0 f (typ.). ? uvlo function detects whether the input voltage sufficient to secure the output voltage of this ic is supplied. and the hysteresis width of 50mv (typ.) is provided to prevent output chattering. fig.23 soft start, shutdown, uvlo timing chart hysteresis 50mv ts s ts s ts s soft start standby mode operating mode standby mode operating mode standby mode operating mode standby mode uvlo en uvlo uvlo v cc en v ou t
7/16 ? short-current protection circuit with time delay function turns off the output to protect the ic from breakdown when the incorporated current limiter is activated continuously for the fixed time(t latch ) or more. the output thus held tuned off may be re covered by restarting en or by re-unlocking uvlo. fig.24 short-current protection circuit with time delay timing chart switching regulator efficiency efficiency ? may be expressed by the equation shown below: efficiency may be improved by reducing the swit ching regulator power dissipation factors p d as follows: dissipation factors: 1) on resistance dissipation of inductor and fet pd(i 2 r) 2) gate charge/discharge dissipation pd(gate) 3) switching dissipation pd(sw) 4) esr dissipation of capacitor pd(esr) 5) operating current dissipation of ic pd(ic) 1)pd(i 2 r)=i out 2 (r coil +r on ) (r coil [ ] dc resistance of inductor, r on [ ] on resistance of fet, i out [a] output current.) 2)pd(gate)=cgs f v (cgs[f] gate capacitance of fet, f[h] switching frequency, v[v] gate driving voltage of fet) 4)pd(esr)=i rms 2 esr (i rms [a] ripple current of capacitor, esr[ ] equivalent series resistance.) 5)pd(ic)=vin i cc (i cc [a] circuit current.) = v out i out vin iin 100[%]= p out pin 100[%]= p out p out +p d 100[%] vin 2 c rss i out f i drive 3)pd(sw)= (c rss [f] reverse transfer capacitance of fet, i drive [a] peak current of gate.) 1/2v out 1mse c output voltage off latch output current in non-control output current in control by limit value (with fall of the output voltage, limit value goes down) en timer latch en standby mode operated mode standby mode operated mode en v out limi t i l until output voltage goes up the half of vo or over, timer latch is not operated. (no timer latch, only limit to the output current)
8/16 consideration on permissible dissipation and heat generation as this ic functions with high efficiency without significant heat generation in most applications, no special consideration is needed on permissible dissipation or heat generation. in case of ex treme conditions, however, including lower input voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation must be carefully considered. for dissipation, only conduction losses due to dc resistance of inductor and on resistance of fe t are considered. because the conduction losses are considered to play the leading role among other dissipation mentioned above including gate charge/discharge dissipation and switching dissipation. if v cc =3.3v, v out =1.8v, r onh =82m , r onl =70m i out =3a, for example, d=v out /v cc =1.8/3.3=0.545 r on =0.545 0.082+(1-0.545) 0.07 =0.0447+0.0319 =0.0766[ ] p=3 2 0.0766 0.6894[w] as r onh is greater than r onl in this ic, the dissipation increases as the on duty becomes greater. with the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed. p=i out 2 r on r on =d r onp +(1-d)r onn d on duty (=v out /v cc ) r onh on resistance of highside mos fet r onl on resistance of lowside mos fet i out output current fig.25 thermal derating curve (vqfn020v4040) power dissipation:pd [w] ambient temperature:ta [ ] 0 25 50 75 100 125 150 0 2.0 3.0 4.0 1.21w 3.56w 1.0 0.70w 0.34w 4 layers (copper foil area : 5505mm 2 ) copper foil in each layers. j-a=35.1 /w 4 layers (copper foil area : 10.29m 2 ) copper foil in each layers. j-a=103.3 /w 4 layers (copper foil area : 10.29m 2 ) j-a=178.6 /w ic only. j -a=367.6 /w 105
9/16 selection of components externally connected 1. selection of inductor (l) current exceeding the current rating of the inductor results in m agnetic saturation of the inductor, which decreases efficiency . the inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating. if v cc =5.0v, v out =2.5v, f=1mhz, i l =0.2 3a=0.6a, for example,(BD8962MUV) select the inductor of low resistance component (such as dcr an d acr) to minimize dissipation in the inductor for better efficiency. 2. selection of output capacitor (c o ) the inductance significantly depe nds on output ripple current. a s seen in the equation (1), the ripple current decreases as the inductor and/or switching frequency increases. i l = (v cc -v out ) v out l v cc f [ a ] ??? ( 1 ) a ppropriate ripple current at output should be 20% more or less of the maximum out p ut current. i l =0.2 i out max. [a] ??? (2) l= (v cc -v out ) v out i l v cc f [ h ] ??? ( 3 ) ( i l : output ripple current, and f: switching frequency) output capacitor should be selected with the consideration on the stability region and the equivalent series resistance re quired to smooth ripple voltage. output ripple voltage is determined by the equation (4) v out = i l esr [v] ??? (4) ( i l : output ripple current, esr: equivalent series resistance of output capacitor) rating of the capacitor should be determined allowing sufficient margin against output voltage. a 22 f to 100 f ceramic capacitor is recommended. less esr allows reduction in output ripple voltage. fig.27 output capacitor ( 5-2.5 ) 2.5 0.6 5 1m l= =2.08 2.2[ h] i l v out fig.26 output ripple current i l v cc il l co v cc l co v out esr
10/16 3. selection of input capacitor (cin) a low esr 22 f/10v ceramic capacitor is recommended to reduce esr di ssipation of input capaci tor for better efficiency. 4. determination of rith, cith that works as a phase compensator as the current mode control is designed to limit a inductor cu rrent, a pole (phase lag) appears in the low frequency area due t o a cr filter consisting of a output capacitor and a load resistanc e, while a zero (phase lead) appears in the high frequency are a due to the output capacitor and its esr. so, the phases are easil y compensated by adding a zero to the power amplifier output with c and r as described below to cancel a pole at the power amplifier. input capacitor to select must be a low esr capacitor of the capacitance sufficient to cope with high ripple current to prevent high transient voltage. the ripple current irms is given by the equation (5): i rms =i out v out ( v cc -v out ) v cc [ a ] ??? ( 5 ) when vcc=2 v out , i rms = i out 2 < worst case > i rms(max.) i rms =2 1.8 ( 3.3-1.8 ) 3.3 =1.49 [ a rms ] gain [db] phase [deg] fig.29 open loop gain characteristics a 0 0 -90 a 0 0 -90 fz(amp.) fig.30 error amp phase compensation characteristics fp= 2 r o c o 1 fz (esr) = 2 e sr c o 1 pole at power amplifie r when the output current decreases, the load resistance ro increases and the pole frequency lowers. fp (min.) = 2 r omax. c o 1 [hz] with lighter load fp (max.) = 2 r omin. c o 1 [hz] with heavier load zero at power amplifie r fz (amp.) = 2 r ith c ith 1 fig.28 input capacitor fp(min.) fp(max.) fz(esr) i out min. i out max. gain [db] phase [deg] v out v cc l co cin increasing capacitance of the out put capacitor lowers the pole frequency while the zero frequency does not change. (this is because when the capacitance is doubled, the capacito r esr reduces to half.) if v cc =3.3v, v out =1.8v, and i outmax.= 3a, (BD8962MUV)
11/16 stable feedback loop may be achieved by canceling the pole fp (mi n.) produced by the output ca pacitor and the load resistance with cr zero correction by the error amplifier. 5. determination of output voltage the output voltage v out is determined by the equation (6): v out =(r2/r1+1) v adj ??? (6) v adj : voltage at adj terminal (0.8v typ.) with r1 and r2 adjusted, the output vo ltage may be determined as required. adjustable output voltage range : 0.8v 2.5v fig.32 determination of output voltage use 1 k ? 100 k ? resistor for r1. if a resistor of the resistance higher than 100 k ? is used, check the assembled set carefully for ripple voltage etc. fig.31 typical application fz (amp.) = fp (min.) 2 r ith c ith 1 = 2 r omax. c o 1 sw 6 1 a dj l co r2 r1 output vo=2.5v vo=2.0v vo=1.8v fig.33 minimum input voltage in each output voltage the lower limit of input voltag e depends on the output voltage. basically, it is recommended to use in the condition : v ccmin = v out +1.2v. fig.33. shows the necessary out put current value at the lowe r limit of input voltage. (dcr of inductor : 20m ) this data is the characteristic va lue, so it? doesn?t guarantee the operation range. 2.7 2.9 3.1 3.3 3.5 3.7 0 1 2 3 input voltage : vcc[v] output current : iout[a] gnd,pgnd sw pv cc en a dj ith v cc v out cin r ith c ith l esr c o r o v out c bst v cc c f r f
12/16 BD8962MUV cautions on pc board layout fig.34 layout diagram lay out the input ceramic capacitor cin closer to the pins pvcc and pgnd, and the output capa citor co closer to the pin pgnd. lay out cith and rith between the pi ns ith and gnd as neat as possible with least necessary wiring. vqfn020v4040 (BD8962MUV) has thermal pad on the reverse of the package. the package thermal performance may be enhanced by bondi ng the pad to gnd plane which take a large area of pcb. recommended components lists on above application symbol part value manufacturer series l coil 2.0uh sumida cdr6d28mnp-2r0nc 2.2uh sumida cdr6d26np-2r2nc c in ceramic capacitor 22uf murata grm32eb11a226ke20 c o ceramic capacitor 22uf murata grm31cb30j226ke18 c ith ceramic capacitor v out =1.0v 1500pf murata crm18 serise v out =1.2v 1000pf murata grm18 serise v out =1.5v 1000pf murata grm18 serise v out =1.8v 560pf murata grm18 serise v out =2.5v 560pf murata grm18 serise r ith resistance v out =1.0v 5.6k rohm mcr03 serise v out =1.2v 6.8k rohm mcr03 serise v out =1.5v 6.8k rohm mcr03 serise v out =1.8v 8.2k rohm mcr03 serise v out =2.5v 12k rohm mcr03 serise cf ceramic capacitor 1000 pf murata grm18 serise rf resistance 10 rohm mcr03 serise c bst ceramic capacitor 0.1 uf murata grm18 serise the parts list presented above is an example of recommended parts. although the parts are sound, actual circuit characteristics should be checked on your application carefully before use. be sure to allow sufficient marg ins to accommoda te variations between external devices and this ic when employing the depicted ci rcuit with other circuit constants modified. both static and transient characteristics should be considered in establishing these margins. when sw itching noise is substantial and may impac t the system, a low pass filter should be inserted between the vcc and pvcc pins, and a schottky barrier diode or snubber established between the sw and pgnd pins.
13/16 i/o equivalence circuit BD8962MUV fig.35 i/o equivalence circuit en ? en pin ? sw pin pv cc sw pv cc pv cc ith ? ith pin v cc ? adj pin a dj pv cc bst ? bst pin pv cc sw
14/16 cautions on use 1. absolute ma ximum ratings while utmost care is taken to quality control of this product, any application that may exc eed some of the absolute maximum ratings including the voltage applied and the operating temperat ure range may result in breakage. if broken, short-mode or open-mode may not be identified. so if it is expected to encounter with special mo de that may exceed the absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses. 2. electrical potential at gnd gnd must be designed to have the lowest elec trical potential in any operating conditions. 3. short-circuiting between terminals, and mismounting when mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. failure to do so may result in ic breakdown. short-circuiting due to foreign matters entered between output terminals, or between output and power supply or gnd may also cause breakdown. 4. thermal shutdown protection circuit thermal shutdown protection circuit is the circuit designed to is olate the ic from thermal runawa y, and not intended to protect and guarantee the ic. so, the ic the the rmal shutdown protection circuit of wh ich is once activated should not be used thereafter for any operation originally intended. 5. inspection with the ic set to a pc board if a capacitor must be connected to the pin of lower impedance dur ing inspection with the ic set to a pc board, the capacitor must be discharged after each process to avoid stress to the ic . for electrostatic protection, provide proper grounding to assembling processes with special care taken in handling and st orage. when connecting to jigs in the inspection process, be sure to turn off the power supply before it is connected and removed. 6. input to ic terminals this is a monolithic ic with p + isolation between p-substrate and each element as illustrated below. this p-layer and the n-layer of each element form a p-n junction, and various parasitic element are formed. if a resistor is joined to a transistor terminal as shown in fig 36. p-n junction works as a parasitic diode if the following rela tionship is satisfied; gnd>terminal a (at resistor side), or gnd>terminal b (at transistor side); and if gnd>terminal b (at npn transistor side), a parasitic npn transistor is activated by n-layer of ot her element adjacent to the above-mentioned parasitic diode. the structure of the ic inevitably forms parasitic elements, the activation of which may cause interference among circuits, and /or malfunctions contributing to breakdown. it is therefore requested to take care not to use the device in su ch manner that the voltage lower than gnd (at p-substrate) ma y be applied to the input terminal, which may result in activation of parasitic elements. fig.36 simplified struct ure of monorisic ic resistor transistor (npn) n n n p + p + p p substrate gnd parasitic element pin a n n p + p + p p substrate gnd parasitic element pin b c b e n gnd pin a p aras iti c element pin b other adjacent elements e b c gnd p aras iti c element
15/16 7. ground wiring pattern if small-signal gnd and large-current gnd are provided, it will be recommended to separate the large-current gnd pattern from t he small-signal gnd pattern and establish a single ground at the refer ence point of the set pcb so that resistance to the wiring p attern and voltage fluctuations due to a large current will cause no fluc tuations in voltages of the small-signal gnd. pay attention n ot to cause fluctuations in the gnd wiring patte rn of external parts as well. 8 . selection of inductor it is recommended to use an inductor with a series resistance element (dcr) 0.1 or less. especially, in case output voltage is set 1.6v or more, note that use of a high dcr inductor will cause an inductor loss, re sulting in decreased output voltage. shou ld this condition continue for a specified period (soft start time + timer latch time), output s hort circuit protection will be ac tivated and output will be latched off. when using an inductor over 0.1 , be careful to ensure adequate margins for variation between external devices and this ic, including transient as well as stat ic characteristics. furthermore, in any case, it is recommende d to start up the output with en after supply voltage is within operation range. ordering part number b d 8 9 6 2 v D e 2 rohm part number type package specification package 62 : ad j ustable ( 0.8 2.5v ) muv : vqfn020v4040 e2 : embossed taping (the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) tape quantity direction of feed embossed carrier tape 2500pcs e2 when you order , please order in times the amount of package quantity. reel direction of feed 1pin 1234 1234 1234 1234 1234 1234 vqfn020v4040 (unit:mm) u m 2.1 0.1 c0.2 0.5 1.0 15 6 10 11 15 16 20 4.0 0.1 4.0 0.1 2.1 0.1 0.4 0.1 0.25 +0.05 -0.04 0.02 +0.03 -0.02 1.0max. (0.22) 0.08 s s
catalog no.08t235a '08.7 rohm ?
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